Taiwan Semiconductor Manufacturing Co. (TSMC) has unveiled a new semiconductor manufacturing technology known as A13, outlining a roadmap aimed at future generations of artificial intelligence systems, high-performance computing platforms, and flagship mobile processors.
The company announced the new process technology during its North America Technology Symposium in Santa Clara, California, stating that A13 is scheduled to enter production in 2029. According to details released by TSMC, the process is designed as a successor to its planned A14 node and will offer improvements in transistor density, power efficiency, and design compatibility.
TSMC said A13 delivers a 6% reduction in chip area compared with A14 while maintaining compatibility with existing A14 design rules. The company said this approach is intended to help chip designers transition more efficiently between process generations without requiring major redesigns.
The announcement comes as demand for advanced semiconductor manufacturing continues to rise across the artificial intelligence and data center sectors. Companies developing AI accelerators and large-scale computing systems increasingly require chips with higher transistor density, improved energy efficiency, and advanced packaging technologies.
TSMC identified artificial intelligence infrastructure, high-performance computing systems, edge computing platforms, and premium smartphones as key target markets for A13.
The company is simultaneously advancing multiple process technologies scheduled for release later this decade. While A13 is positioned as a refinement of A14, TSMC also disclosed additional details about A12, another process node expected around the same period.
Unlike A13, which focuses partly on scaling and compatibility improvements, A12 is expected to introduce a backside power delivery architecture known as “Super Power Rail.” The technology separates power routing from signal routing inside the chip structure, an approach designed to reduce congestion and improve electrical efficiency in large computing processors.
Backside power delivery has become a growing area of focus among semiconductor manufacturers developing processors for artificial intelligence workloads. Modern AI systems require significantly higher power delivery and memory bandwidth than conventional computing chips, increasing pressure on chipmakers to redesign internal power distribution methods.
TSMC’s roadmap reflects broader changes in the semiconductor industry, where performance gains are increasingly tied not only to transistor scaling but also to packaging technologies and chip integration methods.
Alongside the A13 announcement, TSMC outlined plans to expand its advanced packaging capabilities through its CoWoS platform. The company said it intends to support larger multi-die packages capable of integrating approximately 10 compute dies and 20 high-bandwidth memory stacks by 2028.
Advanced packaging has become central to artificial intelligence hardware development as chipmakers shift toward multi-chip designs that combine compute processors and high-bandwidth memory inside a single package. The approach is widely used in modern AI accelerators deployed in cloud computing infrastructure.
TSMC currently manufactures advanced processors for several of the semiconductor industry’s largest customers, including NVIDIA, AMD, and Apple. The company’s process technology roadmap is closely watched because it influences product planning across the broader computing and AI industries.
The announcement also drew attention because TSMC did not commit to using High-NA EUV lithography systems for A13 or A12 production.
High-NA EUV, developed by ASML, is widely viewed as the next major evolution in extreme ultraviolet lithography technology used in advanced semiconductor manufacturing. Several chipmakers, including Intel, have discussed plans to adopt High-NA EUV in future manufacturing nodes.
TSMC executives indicated that the company continues to evaluate how far it can extend current EUV manufacturing techniques before transitioning to High-NA systems. Analysts have noted that High-NA equipment introduces higher manufacturing costs and different design constraints compared with existing EUV tools.
The semiconductor industry is approaching physical and economic limits that make each new process generation more technically demanding and more expensive to deploy. As a result, manufacturers are increasingly combining transistor scaling with advanced packaging, power delivery innovations, and design optimization techniques to improve computing performance.
TSMC’s announcement signals that the company expects strong long-term demand for advanced manufacturing technologies tied to artificial intelligence and high-performance computing markets through the end of the decade.
